GIRD Systems, Inc. offers several ** CO**ordinate

All of GIRD Systems' CORDIC IP cores are available in netlist or source code formats (VHDL). Both formats include bit-accurate MATLAB models; a protected/pre-compiled model is included with the netlist package and full model source code is included with the source code package. A non-disclosure agreement is required to be in place prior to the purchase/release of any source code.

Optionally, our CORDIC IP Cores can support the Advanced eXtensible Interface (AXI 4-Lite) or the Avalon Streaming Interface (Avalon-ST) upon request.

**Summary of Features**

**Pipelined and Serial architectures available to support a wide range of throughput and hardware utilization requirements****Configurable input/output data sample precision, number of iterations****Fixed-point data interface****Utilizes FPGA architecture features (multiplier/DSP blocks, Block RAM, etc.) via inference****Bit-accurate MATLAB model and testbench****VHDL testbench****Available as a netlist and protected model package or with full source code****Basic Technical support**

The Serial and Pipelined Arcsine IP cores calculate the inverse sine of the input argument. By default, the zn output is represented in pi-radian units in the range -1 <= zn < 1 to utilize the full bit width of the output port, but an output range of -pi <= zn < pi can be configured via build-time parameters. A double-iteration algorithm is used to improve the accuracy and correct non-convergence of the estimated arcsine over single-iteration methods. The number of iterations, the input bit width, and the output bit width are build-time configurable parameters.

The Serial and Pipelined Arctangent IP cores calculate the four quadrant inverse tangent of input samples y0/x0. By default, the zn output is represented in pi-radian units in the range -1 <= zn < 1 to utilize the full bit width of the output port, but an output range of -pi <= zn < pi can be configured via build-time parameters. The number of iterations, the input bit width, and the output bit width are build-time configurable parameters.

The Serial and Pipelined Sine/Cosine IP cores produce cosine and sine outputs for an input angle (z0). By default, the z0 input is represented in pi-radian units in the range -1 <= z0 < 1 to utilize the full bit width of the input port, but an input range of -pi <= z0 < pi can be configured via build-time parameters. The number of iterations, the input bit width, and the output bit width are build-time configurable parameters.

The Serial and Pipelined Rotator IP cores rotate complex input samples (x0, y0) by an input angle (z0) and produces complex rotated samples. By default, the z0 input is represented in pi-radian units in the range -1 <= z0 < 1 to utilize the full bit width of the input port, but an input range of -pi <= z0 < pi can be configured via build-time parameters. The number of iterations, the input bit width, and the output bit width are build-time configurable parameters.

For more information or if you have questions or don't see what you're looking for, please __contact us.__

* Data sheets available upon request (__contact us__).

GIRD Systems is a proud partner of __Xilinx Alliance Program__.