Products / FEC IP Cores


LDPC Codec*

Low-Density Parity-Check codes (LDPC) have emerged as the Forward Error Correction method of choice for many cutting-edge wireless communication standards. Due to LDPC code's rising popularity, GIRD Systems, Inc. offers several LDPC Codec IP cores with various architecture options for decoding to cover a wide range of throughput and hardware utilization requirements. LDPC Codec IP core source code was developed in a portable, vendor-agnostic manner and the underlying components of the core were developed to infer and take advantage of hardware features found in many FPGA's from various vendors. The degree of inference of these platform specific features is controlled via vendor-specific tool settings during the synthesis process.

The LDPC Codec IP core has been developed to support a wide range of codeword lengths, code rates, submatrix sizes, check node degrees, and variable node degrees. The application of the LDPC Codec IP core has been focused on the codes specified by the Digital Video Broadcasting - Satellite - Second Generation (DVB-S2) standard. Support for LDPC codes specified by other standards will be made available upon request. Other standards that employ an LDPC Codec include: DVB-S2X, DVB-T2, DVB-C2, GMR-1, IEEE 802.3, IEEE 802.11, IEEE 802.15.3c, IEEE 802.16, IEEE 802.22, CCSDS, CMMB, DTMB, ITU-T, WiMedia 1.5 UWB.

All of GIRD Systems' LDPC Codec IP cores are available in netlist or source code formats (VHDL). Both formats include bit-accurate MATLAB models; a protected/pre-compiled model is included with the netlist package and full model source code is included with the source code package. A non-disclosure agreement is required to be in place prior to the purchase/release of any source code.

Summary of Features

  • Parallel and Serial architectures available to support a wide range of throughput and hardware utilization requirements

  • Supports DVB-S2 code rates and parity check matrices (support for other standards available upon request)

  • Configurable precision of input soft decision, non-linear operations, and variable nodes

  • Fixed-point data interface

  • Utilizes FPGA architecture features (multiplier/DSP blocks, Block RAM, etc.) via inference

  • Bit-accurate MATLAB model and testbench

  • VHDL testbench

  • Available as a netlist and protected model package or with full source code

  • Basic Technical support

Turbo FEC Codec*

GIRD Systems’ Turbo Forward Error Correction (FEC) Codec IP cores includes a 3GPP TS 25.212-compliant encoder and decoder. It implements the parallel concatenated convolutional code (PCCC) class of turbo codes using a traditional encoder and an iterative, soft-in/soft-out (SISO)-based decoder. Additional code rates and non-3GPP frame sizes and interleavers are available upon request.

Optionally, our FEC IP Cores can support the Advanced eXtensible Interface (AXI 4-Lite) or the Avalon Streaming Interface (Avalon-ST) upon request.

Summary of Features

  • Hardware-Agnostic: easily targetable to all major FPGA platforms
  • Supports all 3GPP TS 25.212 frame sizes with dynamic interleaver table generation
  • Supports 1/3 and 1/2 code rates; other code rates available upon request
  • Build-time configurable decoder soft decision data precision
  • Run-time configurable number of decoding iterations

For more information or if you have questions or don't see what you're looking for, please contact us.

* Data sheets available upon request (contact us).

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