Products / Other IP Cores (HDLC, Math, Memory, Misc)


High-Level Data Link Control (HDLC)*

GIRD Systems’ Single-Channel HDLC Controller IP core provides an IEC/ISO 13239:2002(E) compliant High-Level Data Link Control interface for exchanging data between network information sources/sinks. The HDLC IP core provides a synchronous data link layer protocol implementation including opening and close flag insertion, zero insertion and removal, and selectable 16/32-bit CRC calculation and checking.

Optionally, all of GIRD Systems' IP Cores can support the Advanced eXtensible Interface (AXI 4-Lite) or the Avalon Streaming Interface (Avalon-ST) upon request.

Summary of Features

  • Hardware-Agnostic: easily targetable to all major FPGA platforms
  • Provides full duplex IEC/ISO 13239:2002(E) High Level Data Link Control Protocol communications channel
  • Utilizes NRZ-L format for serial transmit/receive clock and serial data
  • Performs either 16-bit or 32-bit frame check sequence
  • Supports clock enabling which allows higher frequency transmit and receive clocks to be used with lower frequency enable strobes

Math IP Cores

GIRD Systems’ suite of Math IP Cores can provide key computational functionality for many designs. Each supports signed and unsigned data formats, has configurable data widths, and supports inference of vendor-specific features (e.g. multiplier/DSP resources). Serial and fully pipelined implementations are availabe for many cores. As with all GIRD Systems' IP cores, they are easily targetable to all major FPGA platforms. Source code is available.

Core Functionality
Adder Tree* Fully pipelined adder tree that finds the sum over all operands
Complex Multiplication* Finds the complex product of two complex operands supporting a configurable number of pipeline stages
Complex Division* Finds the complex quotient of a complex input divisor and complex dividend
Division* Finds the quotient of an input divisor and dividend
Multiplication* Finds the product of two input operands supporting a configurable number of pipeline stages
Power Calculator* Finds the sum of the squares/instantaneous power of a complex signal supporting a configurable number of pipeline stages
Accumulator Bank* Finds an accumulated sum using a configurable number of ganged accumulators

Memory IP Cores

GIRD Systems’ suite of Memory IP Cores have build-time configurable port width and memory depth and support inference of vendor-specific features (e.g. Block RAMs). As with all GIRD Systems' IP cores, they are easily targetable to all major FPGA platforms. Source code is available.

Core Functionality
Dual Port RAM* Infers a simple dual port block RAM with independent read and write ports
True Dual Port RAM* Infers a true dual port RAM with two independent ports that can be read or written
Dual Port ROM* Infers a dual port ROM with two independent read ports; ROM contents are initialized via a text file containing hexadecimal values
FIFO* First In, First Out buffers using inferred block RAMs
Delay Buffer* Delays input samples by a configurable number of cycles; shift register and block RAM-based versions available
Retiming FIFO* First in, First Out Buffer with independent read and write clocks to support clock domain crossing of multi-bit data
Generic Register Map* A parameterizable register map to support external processor interfaces (e.g., general purpose processors, digital signal processors, etc.)
Barrel Shifter* Performs a single cycle permutation of a vector or array of data according to a run-time configurable shift parameter

Miscellaneous Fundamental IP Cores

Core Functionality
Synchronizer* Synchronizes a single clock cycle pulse across clock domains supporting slow-to-fast and fast-to-slow synchronization
Serializer/Deserializer* Converts a parallel data interface into a serial stream of data/converts a serial stream of data into a parallel data interface
Cyclic Redundancy Check (CRC) Calculator* Calculates the CRC of a data stream using a build-time configurable generator polynomial
Pseudo-Random Bit Sequence (PRBS) Generator* Generates a stream of pseudo-random bits using a build-time configurable polynomial
Randomizer* Randomizes the ordering of a sequence of data
Sorting Network* Sorts a small sequence of data using a build-time configurable sorting network architecture for optimal speed/resource tradeoff
Min/Max Detector* Detects the minimum or maximum value over a build-time configurable window of input data

For more information or if you have questions or don't see what you're looking for, please contact us.

* Data sheets available upon request (contact us).

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